Alix/Geode Overclock?

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bogg
DD-WRT Novice


Joined: 12 Jan 2007
Posts: 15

PostPosted: Mon Sep 22, 2008 19:10    Post subject: Alix/Geode Overclock? Reply with quote
Shouldn't the MSR registers be the same as on the OLPC on the Alix boards so that you could easily implement over/under-clocking functions just like on the WRT54G/WRT54GL?

Check this page for further info:

http://xolaptophelp.com/index.php?topic=2389.0
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brabl2
DD-WRT Novice


Joined: 02 Dec 2008
Posts: 1

PostPosted: Tue Dec 02, 2008 8:52    Post subject: Re: Alix/Geode Overclock? Reply with quote
Hi,

I managed to overclock my alix1c (GeodeLX800@500) with Xubuntu 8.10 to 533Mhz(CPU) and 466MHz(GLIU).
At higher frequencies it was VERY unstable.

I used msr-tools - http://www.kernel.org/pub/linux/utils/cpu/msr-tools/ (it is included in ubuntu's main repository)
'rdmsr' and 'wrmsr' have to be run with 'sudo'

I added the script below to /etc/acpi/start.d directory ( sudo gedit /etc/acpi/start.d/99-msr-set-freq.sh )
In /etc/acpi/start.d directory it is not necessary to run it as 'sudo'

The 'sleep 45' is there to change the frequency after start of system is completed (I had problems with BOINC when changing frequency without waiting).

I had also problem that when the frequency was changed from default 500MHz/400MHz directly to 533MHz/466MHz the msr register was written correctly however the real performance was not improved.
So I used the trick, that the frequency is first changed to 333MHz/333MHz and after one second to desired 533MHz/466MHz.
This way the change of frequency is very reliable.

Before running this script it is necessary to read the MSR register 4c000014 and modify the lower 32-bit part of the 64-bit value according to actuall MSR register value (in my case it's 07de002e).

note: 'cat /proc/cpuinfo' shows 500MHz even after successful change of frequency

Complete description of MSR register 4c000014 can be found here:
http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33234F_LX_databook.pdf (page 554)

Maybe it can be hopeful also for your DD-WRT.

brabl2

Code:

#!/bin/sh

echo "sleep 45"
sleep 45

msr_major=202
cpuid_major=203
n=0
mkdir -m 0755 -p /dev/cpu/$n
mknod /dev/cpu/$n/msr -m 0600 c $msr_major $n
mknod /dev/cpu/$n/cpuid -m 0444 c $cpuid_major $n

rdmsr -x 0x4c000014

# 333 MHz / 333MHz
wrmsr 0x4c000014 0x0000049207de002e

rdmsr -x 0x4c000014

echo "sleep 1"
sleep 1

# 500 MHz / 400MHz - original
#wrmsr 0x4c000014 0x0000059c07de002e
# 533 MHz / 400MHz
#wrmsr 0x4c000014 0x0000059e07de002e
# 566 MHz / 400MHz - not working
#wrmsr 0x4c000014 0x000005a007de002e

# 533 MHz / 433MHz
#wrmsr 0x4c000014 0x0000061e07de002e
# 566 MHz / 433MHz - not working
#wrmsr 0x4c000014 0x0000062007de002e

# 533 MHz / 466MHz
#wrmsr 0x4c000014 0x0000069e07de002e
# 533 MHz / 466MHz + PCI_SEMI_SYNC_MODE
wrmsr 0x4c000014 0x0000069e07de012e

# 533 MHz / 500MHz - not working
#wrmsr 0x4c000014 0x0000071e07de002e

rdmsr -x 0x4c000014

#cat /proc/cpuinfo | grep MHz

# [43:39] GLIUMULT
# GLIU Multiplier (Bootstrap Dependent, see Table 6-87).
# 00000: Multiply by 1,....
# 11111: Multiply by 32.

# [38]   GLIUDIV 
# GLIU Divide. When set, predivide the GLIU PLL input frequency by 2.
# 0: Do not predivide input. (Default)
# 1: Divide by 2.

# [37:33] COREMULT
# CPU Core Multiplier (bootstrap dependent, see Table 6-87 on page 556).
# 00000: Multiply by 1,....
# 11111: Multiply by 32.

# [32]   COREDIV 
# CPU Core Divide. When set, predivide the GLIU PLL input frequency by 2.
# 0: Do not predivide input. (Default)
# 1: Divide by 2.

# [9] VA_SEMI_SYNC_MODE 
# CPU Sync Mode. This bit controls whether the CPU uses a FIFO for interfacing with the
# GLIU. If the bit is high, the CPU will not use the FIFO. It behaves as if the CPU and GLIU
# domains are synchronous. This bit can be set high as long as the CPU and GLIU fre-
# quencies are multiples of each other. The bit is always reset low.

# [8] PCI_SEMI_SYNC_MODE
# PCI Sync Mode. This bit controls whether the PCI uses the falling edges of mb_func_clk
# and pci_func_clk for interfacing with GLIU or not. If the bit is high, PCI does not use fall-
# ing clock edges. It behaves as if the PCI and GLIU domains are synchronous. This bit
# can be set high as long as the PCI and GLIU frequencies are multiples of each other. The
# bit always resets low.
Sash
DD-WRT Guru


Joined: 20 Sep 2006
Posts: 17619
Location: Hesse/Germany

PostPosted: Sat Nov 23, 2013 18:24    Post subject: Reply with quote
since we dont have the msr-tools yet it wont work..but anyway : http://www.dd-wrt.com/wiki/index.php/PC-Engines#Overclocking_Alix
and
http://svn.dd-wrt.com/ticket/3092

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